In data transmission systems (transmission apparatuses), known is a cyclic redundancy check (CRC) method as a method of determining whether an error is present in received data (for example, see Japanese Laid-open Patent Publication Nos. 2001-308720 and 2001-358594). In the CRC method, a transmitter transmits a frame signal in which a frame check sequence (FCS), into which a CRC code obtained by calculating the data is embedded, is added to data to be transmitted. Meanwhile, a receiver calculates data that is extracted from the received frame signal to generate a CRC code, and determines that no error is present in the transmitted data when the generated CRC code matches the CRC code that is embedded into the FCS.
To achieve high speed calculation for generating a CRC code, known is a method in which a received frame signal is serial-parallel converted, and the serial-parallel converted data is calculated (for example, see Japanese Laid-open Patent Publication Nos. 2009-55407, 2003-46393, and 2002-359561).
When a frame signal that includes packets having different bit lengths is serial-parallel converted and calculated, a CRC code is generated using CRC code calculation circuits in accordance with the bit lengths of the respective packets. However, there has been a problem in that in a case of generating a CRC code using CRC code calculation circuits in accordance with the bit lengths, when a serial-parallel converted packet has a long bit length, the number of the CRC code calculation circuits to be arranged is increased, leading to an increase in the size of the circuit.
One embodiment aims to provide a CRC code calculation circuit capable of calculating packets that are parallel signals having different bit lengths, with a comparatively small-sized circuit size, and generating a CRC code.